Crosstalk is caused by capacitive coupling from one part of a circuit to another, causing noise or delay error. When evaluating the effect of crosstalk, the circuit which is being evaluated is referred to as the ‘victim’ while the circuits whose effects on the ‘victim’ are measured are referred to as ‘aggressors’. In the presence of crosstalk, timing is affected by secondary nets (e.g. aggressors) and timing analysis usually takes multiple iterations.
As integrated circuit designs have become larger and larger, certain computer-aided design tools utilize models in order to quickly perform timing analysis of the constituent circuitry comprising a given block. Examples include ILMs (interface logic models) and ETMs (extracted timing models). The use of models functions by reducing the static timing analysis runtimes and the memory it uses to more manageable levels.
However, there are problems regarding the use of models in a hierarchical design flow. One problem involves the fact that the various functional blocks comprising a hierarchical design are allocated timing budgets. The timing budgets are intended to reflect the relative contribution of the timing of a particular block to the overall timing performance of the integrated circuit design. In practice, such budgets are difficult to establish accurately. Another problem involves the fact that it is difficult to manage and merge the timing constraints of lower-level blocks with the constraints of top-level blocks. For example, constraints of coupled blocks are often particularly uncertain until the constraints of lower-level blocks have been firmly established.
The above problems and more, lead to chip designers having a general lack of confidence in the static timing analysis results obtained using hierarchical design flows. One conventional solution is to flatten a hierarchical design such that it is represented as a single monolithic integrated circuit design (e.g., no blocks or modeling) and run conventional static timing analysis on the flattened design. Once again, the problem with this solution is that as designs get larger runtime can extend into several days and require very expensive computer systems with very large memory sizes.